Abstract
An architecture based on scalable binary tree consisting of splitter/ combiners for address translation of optical symmetric multiprocessor (SMP), was proposed. The architecture featured optical time division multiplexing involving dual Y-junction splitter/combiner for backplane and on-board interconnections. The designs of 1x8 splitter with loss of 8.325dB for backplane and 1x4 splitters with losses of 6.53 dB for onboard interconnection were presented. The optical SMP network provides distinct performance and cost advantages over traditional electronic interconnect and other optical interconnection networks.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 865-866 |
| Number of pages | 2 |
| Journal | Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting-LEOS |
| Volume | 2 |
| State | Published - 2001 |
| Event | 14th Annual Meeting of the IEEE Lasers and Electro-Optics Society - San Diego, CA, United States Duration: Nov 11 2001 → Nov 15 2001 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering