TY - GEN
T1 - WL-Emap
T2 - 8th Southern Programmable Logic Conference, SPL 2012
AU - Chávez, Rodrigo Savage
AU - Rajavel, Senthilkumar Thoravi
AU - Akoglu, Ali
N1 - Funding Information:
Supported by the Ministry of Agriculture of the Czech Republic, Project No. NAZV QJ1610186.
PY - 2012
Y1 - 2012
N2 - Technology mapping is the first stage of the process of porting an application onto Field Programmable Gate Array (FPGA) architecture. This stage is highly critical as it sets the constraints of its successor stages of clustering, placement and routing. Intrinsic Shortest Path Length (ISPL) has been shown to accurately predict the post placement individual net length information for a given net list. In this study, we introduce the WL-Emap by replacing the switching activity based cut selection cost function of the Emap technology mapping algorithm with the wirelength factor based cost function. WL-Emap improves the channel width by 13.13% with a critical path delay overhead of 1.6% for the combinatorial MCNC benchmarks, and by 15.79% with a critical path delay overhead of 6.95% for all the 20 MCNC benchmarks using cluster size 4 over Emap. WL-Emap achieves over 15% channel width reduction performance with respect to the well-known technology mapping algorithms Flowmap, CutMap and WireMap.
AB - Technology mapping is the first stage of the process of porting an application onto Field Programmable Gate Array (FPGA) architecture. This stage is highly critical as it sets the constraints of its successor stages of clustering, placement and routing. Intrinsic Shortest Path Length (ISPL) has been shown to accurately predict the post placement individual net length information for a given net list. In this study, we introduce the WL-Emap by replacing the switching activity based cut selection cost function of the Emap technology mapping algorithm with the wirelength factor based cost function. WL-Emap improves the channel width by 13.13% with a critical path delay overhead of 1.6% for the combinatorial MCNC benchmarks, and by 15.79% with a critical path delay overhead of 6.95% for all the 20 MCNC benchmarks using cluster size 4 over Emap. WL-Emap achieves over 15% channel width reduction performance with respect to the well-known technology mapping algorithms Flowmap, CutMap and WireMap.
KW - FPGA
KW - routability
KW - technology mapping
KW - wirelength prediction
UR - http://www.scopus.com/inward/record.url?scp=84863889193&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84863889193&partnerID=8YFLogxK
U2 - 10.1109/SPL.2012.6211800
DO - 10.1109/SPL.2012.6211800
M3 - Conference contribution
AN - SCOPUS:84863889193
SN - 9781467301862
T3 - SPL 2012 - 8th Southern Programmable Logic Conference
BT - SPL 2012 - 8th Southern Programmable Logic Conference
Y2 - 20 March 2012 through 23 March 2012
ER -