@inproceedings{5e477c0d11654b96b443643360db50d6,
title = "Using domain partitioning in wrapper design for IP cores under power constraints",
abstract = "This paper presents a novel design method for power-aware test wrappers targeting embedded cores with multiple clock domains. We show that effective partitioning of clock domains combined with bandwidth conversion and gated-clocks would yield shorter test times due to greater flexibility when determining optimal test schedules especially under tight power constraints.",
keywords = "Embedded core test, Multi-clock domain, SoC, Test scheduling, Wrapper design",
author = "Yu, \{Thomas Edison\} and Tomokazu Yoneda and Danella Zhao and Hideo Fujiwara",
year = "2007",
doi = "10.1109/VTS.2007.86",
language = "English (US)",
isbn = "0769528120",
series = "Proceedings of the IEEE VLSI Test Symposium",
pages = "369--374",
booktitle = "Proceedings - 25th IEEE VLSI Test Symposium, VTS'07",
note = "25th IEEE VLSI Test Symposium, VTS'07 ; Conference date: 06-05-2007 Through 10-05-2007",
}