Unscheduling, Unpredication, Unspeculation: Reverse Engineering Itanium Executables

Noah Snavely, Saumya Debray, Gregory Andrews

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations


EPIC (Explicitly Parallel Instruction Computing) architectures, exemplified by the Intel Itanium, support a number of advanced architectural features, such as explicit instruction-level parallelism, instruction predication, and speculative loads from memory. However, compiler optimizations to take advantage of such architectural features can profoundly restructure the program's code, making it potentially difficult to reconstruct the original program logic from an optimized Itanium executable. This paper describes techniques to undo some of the effects of such optimizations and thereby improve the quality of reverse engineering such executables.

Original languageEnglish (US)
Number of pages10
StatePublished - 2003
Externally publishedYes
EventTenth Working Conference on Reverse Engineering - Victoria, BC, Canada
Duration: Nov 13 2003Nov 16 2003


ConferenceTenth Working Conference on Reverse Engineering
CityVictoria, BC

ASJC Scopus subject areas

  • General Engineering


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