TY - JOUR
T1 - Ultracompact and Low-Power Logic Circuits via Workfunction Engineering
AU - Canan, Talha F.
AU - Kaya, Savas
AU - Karanth, Avinash
AU - Louri, Ahmed
N1 - Funding Information:
This work was supported in part by the National Science Foundation under Grant CCF-1054339 (CAREER), Grant CCF-1513606, Grant CCF-1547035, and Grant CCF-1547036. The work of Talha F. Canan was supported by the Nanoscale and Quantum Phenomena Institute, Ohio Universit
Funding Information:
1School of Electrical Engineering and Computer Science, Ohio University, Athens, OH 45701 USA 2Department of Electrical and Computer Engineering, George Washington University, Washington, DC 20052 USA CORRESPONDING AUTHOR: S. KAYA (kaya@ohio.edu) This work was supported in part by the National Science Foundation under Grant CCF-1054339 (CAREER), Grant CCF-1513606, Grant CCF-1547035, and Grant CCF-1547036. The work of Talha F. Canan was supported by the Nanoscale and Quantum Phenomena Institute, Ohio University. This article has supplementary downloadable material available at http://ieeexplore.ieee.org, provided by the authors.
Publisher Copyright:
© 2014 IEEE.
PY - 2019/12
Y1 - 2019/12
N2 - An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to × 10 ) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance.
AB - An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to × 10 ) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance.
KW - 3T-XOR
KW - 4T AND-OR-invert (AOI)
KW - 6T 4-to-1 multiplexer (MUX)
KW - ambipolar
KW - CMOS logic gates
KW - nanotechnology
KW - Schottky-barrier MOSFET
KW - tunneling
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U2 - 10.1109/JXCDC.2019.2962494
DO - 10.1109/JXCDC.2019.2962494
M3 - Article
AN - SCOPUS:85077278472
VL - 5
SP - 94
EP - 102
JO - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
JF - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
SN - 2329-9231
IS - 2
M1 - 8943278
ER -