Abstract
The design of a parallel processor containing 60 32-bit processors with on-chip floating point hardware, 60 Mbytes of memory, hardware random number generation, and a high bandwidth, reconfigurable interprocessor communications system is discussed. The system is especially well- suited to run Monte Carlo-based algorithms, such as simulated annealing, for optimization and estimation problems in nuclear medicine and other areas.
Original language | English (US) |
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Pages (from-to) | 619-624 |
Number of pages | 6 |
Journal | Proceedings of SPIE - The International Society for Optical Engineering |
Volume | 1092 |
DOIs | |
State | Published - May 25 1989 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Computer Science Applications
- Applied Mathematics
- Electrical and Electronic Engineering