Three-dimensional stacked nanophotonic network-on-chip architecture with minimal reconfiguration

Randy W. Morris, Avinash Karanth Kodi, Ahmed Louri, Ralph D. Whaley

Research output: Contribution to journalArticlepeer-review

38 Scopus citations


As throughput, scalability, and energy efficiency in network-on-chips (NoCs) are becoming critical, there is a growing impetus to explore emerging technologies for implementing NoCs in future multicore and many-core architectures. Two disruptive technologies on the horizon are nanophotonic interconnects (NIs) and 3D stacking. NIs can deliver high on-chip bandwidth while delivering low energy/bit, thereby providing a reasonable performance-per-watt in the future. Three-dimensional stacking can reduce the interconnect distance and increase the bandwidth density by incorporating multiple communication layers. In this paper, we propose an architecture that combines NIs and 3D stacking to design an energy-efficient and reconfigurable NoC. We quantitatively compare the hardware complexity of the proposed topology to other nanophotonic networks in terms of hop count, network diameter, radix, and photonic parameters. To maximize performance, we also propose an efficient reconfiguration algorithm that dynamically reallocates channel bandwidth by adapting to traffic fluctuations. For 64-core reconfigured network, our simulation results indicate that the execution time can be reduced up to 25 percent for Splash-2, PARSEC, and SPEC CPU2006 benchmarks. Moreover, for a 256 - core version of the proposed architecture, our simulation results indicate a throughput improvement of more than 25 percent and energy savings of 23 percent on synthetic traffic when compared to competitive on-chip electrical and optical networks.

Original languageEnglish (US)
Article number6256662
Pages (from-to)243-255
Number of pages13
JournalIEEE Transactions on Computers
Issue number1
StatePublished - Jan 2014


  • 3D stacking
  • CMP
  • Nanophotonics
  • NoC
  • Reconfigurable

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


Dive into the research topics of 'Three-dimensional stacked nanophotonic network-on-chip architecture with minimal reconfiguration'. Together they form a unique fingerprint.

Cite this