Abstract
Void formation and growth is a major problem for solder interface materials, because they impede heat conduction from the silicon die to heat spreader/heat sink in semiconductor electronic devices. This work uses infrared microscopy to measure temperature distributions on the interfacial layer through the silicon die. Hot spots, with a 15°C temperature rise above average die temperature, are found right on top of void-like inclusions at a device power density above 50 W/cm 2. The technique presented in the manuscript, with a theoretical spatial resolution of 3-5μm, is promising for thermal characterization of voids in interface solder layers.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 98-103 |
| Number of pages | 6 |
| Journal | Annual IEEE Semiconductor Thermal Measurement and Management Symposium |
| Volume | 20 |
| State | Published - 2004 |
| Externally published | Yes |
| Event | 20th Annual IEEE Semiconductor Thermal Measurement and Management Symposium - Proceedings 2004 - San Jose, CA., United States Duration: Mar 9 2004 → Mar 11 2004 |
Keywords
- Solder die-attach
- Thermal contact resistance
- Through-wafer infrared microscopy
- Void formation and growth
ASJC Scopus subject areas
- Instrumentation
- Electrical and Electronic Engineering