Abstract
The complexity of embedded applications has led to highly configurable algorithms and standards that support a wide range of data inputs. Design time optimization of these algorithms is not possible due to combinatorial explosion of data configurations - or data profiles - that can be observed at runtime. To address these challenges, data adaptable design methodologies can be utilized to directly model the correlation of data profiles and algorithmic requirements. This approach enables a reconfigurable implementation that adapts the system execution at runtime to utilize profile-specific hardware tasks in response to changes in the data profile of the current input data. In this paper, we present a simulation-based methodology and heuristic search methodology for determining system configurations considering available hardware accelerators and the sizes of FIFO queues within those accelerators to determine Pareto optimal configurations for system throughput and area. We further present a hardware/software communication wrapper and middleware to support seamless communication between software and hardware tasks.
Original language | English (US) |
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Pages | 59-68 |
Number of pages | 10 |
DOIs | |
State | Published - 2013 |
Externally published | Yes |
Event | 20th Annual IEEE International Conference and Workshops on the Engineering of Computer Based Systems, ECBS 2013 - Phoenix, AZ, United States Duration: Apr 22 2013 → Apr 24 2013 |
Other
Other | 20th Annual IEEE International Conference and Workshops on the Engineering of Computer Based Systems, ECBS 2013 |
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Country/Territory | United States |
City | Phoenix, AZ |
Period | 4/22/13 → 4/24/13 |
Keywords
- Data adaptability
- hardware/software codesign
- hardware/software communication middleware
- model-based design
ASJC Scopus subject areas
- General Computer Science
- Control and Systems Engineering