@inproceedings{c5f3f584eb7e47d9a31f68c55cab87ad,
title = "Symbolic analysis of faulty logic circuits in the presence of correlated gate failures",
abstract = "In this paper we present a method for symbolic analysis of unreliable logic circuits in the presence of correlated and data-dependent gate failures, described by Markov chains. Presented probabilistic algorithm is used for the analysis of majority logic and XOR logic circuits.",
keywords = "Combinatorial circuits, Markov chains, fault-tolerance, symbolic analysis",
author = "Srdjan Brkic and Predrag Ivanis and Goran Djordjevic and Bane Vasic",
year = "2013",
doi = "10.1109/TELFOR.2013.6716246",
language = "English (US)",
isbn = "9781479914197",
series = "2013 21st Telecommunications Forum Telfor, TELFOR 2013 - Proceedings of Papers",
pages = "369--372",
booktitle = "2013 21st Telecommunications Forum Telfor, TELFOR 2013 - Proceedings of Papers",
note = "2013 21st Telecommunications Forum Telfor, TELFOR 2013 ; Conference date: 26-11-2013 Through 28-11-2013",
}