@inproceedings{3881e05214b64853a2fc05c385d27085,
title = "Statistical clock tree routing for robustness to process variations",
abstract = "Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufacturing performance. Process-induced skew presents an ever-growing limitation for high speed, large area clock networks. To achieve multi-GHz operation for high-end designs, clock networks must be constructed to tolerate variations in various interconnect parameters. We propose a statistical centering based clock routing algorithm built upon DME that greatly improves skew tolerance to interconnect variations. The algorithm achieves the improvement by: i) choosing the best center measure which is dynamically based on the first three moments of the skew distribution, and ii) designing for all sink pairs in the subtrees simultaneously. In addition, a variation aware abstract topology generation algorithm is proposed in this paper. Experiments on benchmark circuits demonstrate the efficiency of the proposed method in reducing the number of skew violations by 12%-37%.",
keywords = "Clock Tree, Process Variations, Robustness, Routing",
author = "Uday Padmanabhan and Wang, {Janet M.} and Jiang Hu",
year = "2006",
doi = "10.1145/1123008.1123037",
language = "English (US)",
isbn = "1595932992",
series = "Proceedings of the International Symposium on Physical Design",
publisher = "Association for Computing Machinery (ACM)",
pages = "149--156",
booktitle = "Proceedings of ISPD'06 - 2006 International Symposium on Physical Design",
note = "ISPD'06 - 2006 International Symposium on Physical Design ; Conference date: 09-04-2006 Through 12-04-2006",
}