Statistical clock tree routing for robustness to process variations

Uday Padmanabhan, Janet M. Wang, Jiang Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations


Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufacturing performance. Process-induced skew presents an ever-growing limitation for high speed, large area clock networks. To achieve multi-GHz operation for high-end designs, clock networks must be constructed to tolerate variations in various interconnect parameters. We propose a statistical centering based clock routing algorithm built upon DME that greatly improves skew tolerance to interconnect variations. The algorithm achieves the improvement by: i) choosing the best center measure which is dynamically based on the first three moments of the skew distribution, and ii) designing for all sink pairs in the subtrees simultaneously. In addition, a variation aware abstract topology generation algorithm is proposed in this paper. Experiments on benchmark circuits demonstrate the efficiency of the proposed method in reducing the number of skew violations by 12%-37%.

Original languageEnglish (US)
Title of host publicationProceedings of ISPD'06 - 2006 International Symposium on Physical Design
PublisherAssociation for Computing Machinery (ACM)
Number of pages8
ISBN (Print)1595932992, 9781595932990
StatePublished - 2006
EventISPD'06 - 2006 International Symposium on Physical Design - San Jose, CA, United States
Duration: Apr 9 2006Apr 12 2006

Publication series

NameProceedings of the International Symposium on Physical Design


OtherISPD'06 - 2006 International Symposium on Physical Design
Country/TerritoryUnited States
CitySan Jose, CA


  • Clock Tree
  • Process Variations
  • Robustness
  • Routing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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