TY - GEN
T1 - Sparsity-Aware Hardware-Software Co-Design of Spiking Neural Networks
T2 - 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2024
AU - Aliyev, Ilkin
AU - Svoboda, Kama
AU - Adegbija, Tosiron
AU - Fellous, Jean Marc
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Spiking Neural Networks (SNNs) are inspired by the sparse and event-driven nature of biological neural processing, and offer the potential for ultra-low-power artificial intelligence. However, realizing their efficiency benefits requires specialized hardware and a co-design approach that effectively leverages sparsity. We explore the hardware-software co-design of sparse SNNs, examining how sparsity representation, hardware architectures, and training techniques influence hardware efficiency. We analyze the impact of static and dynamic sparsity, discuss the implications of different neuron models and encoding schemes, and investigate the need for adaptability in hardware designs. Our work aims to illuminate the path towards embedded neuro-morphic systems that fully exploit the computational advantages of sparse SNNs.
AB - Spiking Neural Networks (SNNs) are inspired by the sparse and event-driven nature of biological neural processing, and offer the potential for ultra-low-power artificial intelligence. However, realizing their efficiency benefits requires specialized hardware and a co-design approach that effectively leverages sparsity. We explore the hardware-software co-design of sparse SNNs, examining how sparsity representation, hardware architectures, and training techniques influence hardware efficiency. We analyze the impact of static and dynamic sparsity, discuss the implications of different neuron models and encoding schemes, and investigate the need for adaptability in hardware designs. Our work aims to illuminate the path towards embedded neuro-morphic systems that fully exploit the computational advantages of sparse SNNs.
KW - energy efficiency
KW - event-driven processing
KW - hardware-software co-design
KW - sparsity
KW - Spiking Neural Networks (SNNs)
UR - http://www.scopus.com/inward/record.url?scp=85217082819&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85217082819&partnerID=8YFLogxK
U2 - 10.1109/MCSoC64144.2024.00074
DO - 10.1109/MCSoC64144.2024.00074
M3 - Conference contribution
AN - SCOPUS:85217082819
T3 - Proceedings - 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2024
SP - 413
EP - 420
BT - Proceedings - 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2024
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 16 December 2024 through 19 December 2024
ER -