Single-chip, asynchronous echo canceller for high-speed data communication

Richard P. Mackey; Jeffrey J. Rodriguez; Jo Dale Carothers; Sarma B.K. Vrudhula

Single-chip, asynchronous echo canceller for high-speed data communication

Richard P. Mackey
, Jeffrey J. Rodriguez
, Jo Dale Carothers
, Sarma B.K. Vrudhula

Research output: Contribution to journal › Conference article › peer-review

Abstract

A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.

Original language	English (US)
Pages (from-to)	181-184
Number of pages	4
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
State	Published - 1995
Event	Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA Duration: Sep 18 1995 → Sep 22 1995

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@article{fbeed7514b30493a96f1881a0a6a290b,

title = "Single-chip, asynchronous echo canceller for high-speed data communication",

abstract = "A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.",

author = "Mackey, \{Richard P.\} and Rodriguez, \{Jeffrey J.\} and Carothers, \{Jo Dale\} and Vrudhula, \{Sarma B.K.\}",

year = "1995",

language = "English (US)",

pages = "181--184",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

issn = "1063-0988",

note = "Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit ; Conference date: 18-09-1995 Through 22-09-1995",

}

TY - JOUR

T1 - Single-chip, asynchronous echo canceller for high-speed data communication

AU - Mackey, Richard P.

AU - Rodriguez, Jeffrey J.

AU - Carothers, Jo Dale

AU - Vrudhula, Sarma B.K.

PY - 1995

Y1 - 1995

N2 - A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.

AB - A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.

UR - https://www.scopus.com/pages/publications/0029539521

UR - https://www.scopus.com/pages/publications/0029539521#tab=citedBy

M3 - Conference article

AN - SCOPUS:0029539521

SN - 1063-0988

SP - 181

EP - 184

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

T2 - Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit

Y2 - 18 September 1995 through 22 September 1995

ER -

Single-chip, asynchronous echo canceller for high-speed data communication

Abstract

ASJC Scopus subject areas

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