TY - GEN
T1 - Self-optimization of performance-per-watt for interleaved memory systems
AU - Khargharia, Bithika
AU - Hariri, Salim
AU - Yousif, Mazin S.
PY - 2007
Y1 - 2007
N2 - With the increased complexity of platforms coupled with data centers' servers sprawl, power consumption is reaching unsustainable limits. Memory is an important target for platform-level energy efficiency, where most power management techniques use multiple power state DRAM devices to transition them to low-power states when they are "sufficiently" idle. However, fully-interleaved memory in high-performance servers presents a research challenge to the memory power management problem. Due to data striping across all memory modules, memory accesses are distributed in a manner that considerably reduces the idleness of memory modules to warrant transitions to low-power states. In this paper we introduce a novel technique for dynamic memory interleaving that is adaptive to incoming workload in a manner that reduces memory energy consumption while maintaining the performance at an acceptable level. We use optimization theory to formulate and solve the powerperformance management problem. We use dynamic cache line migration techniques to increase the idleness of memory modules by consolidating the application's working-set on a minimal set of ranks. Our technique yields energy saving of about 48.8 % (26.7 kJ) compared to traditional techniques measured at 4.5%. It delivers the maximum performance-per-watt during all phases of the application execution with a maximum performance-per-watt improvement of 88.48%.
AB - With the increased complexity of platforms coupled with data centers' servers sprawl, power consumption is reaching unsustainable limits. Memory is an important target for platform-level energy efficiency, where most power management techniques use multiple power state DRAM devices to transition them to low-power states when they are "sufficiently" idle. However, fully-interleaved memory in high-performance servers presents a research challenge to the memory power management problem. Due to data striping across all memory modules, memory accesses are distributed in a manner that considerably reduces the idleness of memory modules to warrant transitions to low-power states. In this paper we introduce a novel technique for dynamic memory interleaving that is adaptive to incoming workload in a manner that reduces memory energy consumption while maintaining the performance at an acceptable level. We use optimization theory to formulate and solve the powerperformance management problem. We use dynamic cache line migration techniques to increase the idleness of memory modules by consolidating the application's working-set on a minimal set of ranks. Our technique yields energy saving of about 48.8 % (26.7 kJ) compared to traditional techniques measured at 4.5%. It delivers the maximum performance-per-watt during all phases of the application execution with a maximum performance-per-watt improvement of 88.48%.
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U2 - 10.1007/978-3-540-77220-0_35
DO - 10.1007/978-3-540-77220-0_35
M3 - Conference contribution
AN - SCOPUS:38349074505
SN - 9783540772194
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 368
EP - 380
BT - High Performance Computing - HiPC 2007 - 14th International Conference, Proceedings
PB - Springer-Verlag
T2 - 14th International Conference on High-Performance Computing, HiPC 2007
Y2 - 18 December 2007 through 21 December 2007
ER -