TY - GEN
T1 - Securing On-Chip Learning
T2 - 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024
AU - Nazari, Najmeh
AU - Gubbi, Kevin Immanuel
AU - Latibari, Banafsheh Saber
AU - Chowdhury, Muhtasim Alam
AU - Fang, Chongzhou
AU - Sasan, Avesta
AU - Rafatirad, Setareh
AU - Homayoun, Houman
AU - Salehi, Soheil
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - On-chip learning is the process of training or updating machine learning models directly on specialized hardware. This approach differs from traditional machine learning, which typically conducts training on external computing resources like Central Processing Units (CPUs) or Graphics Processing Units (GPUs). On-chip learning offers several advantages, including reduced latency, improved energy efficiency, enhanced privacy, and adaptability. Consequently, it holds great promise for enabling intelligent decision-making and adaptability in resource-constrained edge and IoT devices while addressing privacy concerns. In Spiking Neural Network (SNN), on-chip learning is enabled by adjusting synaptic weights, allowing the network's behavior to dynamically align with desired outcomes. However, this adaptability may introduce potential security vulnerabilities. Unmitigated security risks in on-chip learning can lead to various threats, including data leaks, unauthorized access, and even adversarial manipulation of the learning process. This manuscript aims to provide a comprehensive overview of the security risks associated with on-chip learning, with a focus on potential vulnerabilities within the SNN architecture. We will explore real-world scenarios where these vulnerabilities can be exploited and outline protective measures and mitigation strategies to address these security concerns.
AB - On-chip learning is the process of training or updating machine learning models directly on specialized hardware. This approach differs from traditional machine learning, which typically conducts training on external computing resources like Central Processing Units (CPUs) or Graphics Processing Units (GPUs). On-chip learning offers several advantages, including reduced latency, improved energy efficiency, enhanced privacy, and adaptability. Consequently, it holds great promise for enabling intelligent decision-making and adaptability in resource-constrained edge and IoT devices while addressing privacy concerns. In Spiking Neural Network (SNN), on-chip learning is enabled by adjusting synaptic weights, allowing the network's behavior to dynamically align with desired outcomes. However, this adaptability may introduce potential security vulnerabilities. Unmitigated security risks in on-chip learning can lead to various threats, including data leaks, unauthorized access, and even adversarial manipulation of the learning process. This manuscript aims to provide a comprehensive overview of the security risks associated with on-chip learning, with a focus on potential vulnerabilities within the SNN architecture. We will explore real-world scenarios where these vulnerabilities can be exploited and outline protective measures and mitigation strategies to address these security concerns.
KW - AI Accelerator
KW - Cross-Layer Security
KW - Machine Learning Hardware
KW - On-Chip Learning
KW - Spiking Neural Networks
UR - https://www.scopus.com/pages/publications/85198539682
UR - https://www.scopus.com/pages/publications/85198539682#tab=citedBy
U2 - 10.1109/ISCAS58744.2024.10558041
DO - 10.1109/ISCAS58744.2024.10558041
M3 - Conference contribution
AN - SCOPUS:85198539682
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - ISCAS 2024 - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 19 May 2024 through 22 May 2024
ER -