SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning

Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Prior studies have shown that the retention time of the non-volatile spin-transfer torque RAM (STT-RAM) can be relaxed in order to reduce STT-RAM's write energy and latency. However, since different applications may require different retention times, STT-RAM retention times must be critically explored to satisfy various applications' needs. This process can be challenging due to exploration overhead, and exacerbated by the fact that STT-RAM caches are emerging and are not readily available for design time exploration. This paper explores using known and easily obtainable statistics (e.g., SRAM statistics) to predict the appropriate STT-RAM retention times, in order to minimize exploration overhead. We propose an STT-RAM Cache Retention Time (SCART) model, which utilizes machine learning to enable design time or runtime prediction of right-provisioned STT-RAM retention times for latency or energy optimization. Experimental results show that, on average, SCART can reduce the latency and energy by 20.34% and 29.12%, respectively, compared to a homogeneous retention time while reducing the exploration overheads by 52.58% compared to prior work.

Original languageEnglish (US)
Title of host publication2019 10th International Green and Sustainable Computing Conference, IGSC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728154169
DOIs
StatePublished - Oct 2019
Event10th International Green and Sustainable Computing Conference, IGSC 2019 - Alexandria, United States
Duration: Oct 21 2019Oct 24 2019

Publication series

Name2019 10th International Green and Sustainable Computing Conference, IGSC 2019

Conference

Conference10th International Green and Sustainable Computing Conference, IGSC 2019
Country/TerritoryUnited States
CityAlexandria
Period10/21/1910/24/19

Keywords

  • Spin-Transfer Torque RAM (STT-RAM) cache
  • adaptable hardware
  • configurable memory
  • low-power embedded systems
  • retention time.

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture
  • Renewable Energy, Sustainability and the Environment

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