Scalable three-dimensional optical interconnects for data centers

Technology scaling has paved the way to integrate hundreds and probably thousands of cores on a single-chip in the future. As the numbers of cores increases, energy efficiency and scalability of Network-on-Chips(NoCs) has become a critical challenge that could potentially hinder the performance of future warehouse scale computers (WSC) or datacenters. Emerging technologies such as silicon photonics and 3D stacking are currently being explored to overcome the drawbacks of traditional metallic interconnects for on-chip networks. In this chapter, we combine 3D stacking and silicon photonics to deliver high on-chip bandwidth and low energy/bit to achieve a high throughput, reconfigurable, energy efficient photonic NoC fabric. We propose to develop a multi-layer photonic interconnect that can dynamically reconfigure without system intervention and allocate channel bandwidth from less utilized links to more utilized communication links. In addition, we propose a Power Reduction Technique (PRT) that dynamically deactivates photonic interconnects that are idle and reduce power dissipation. For 64-core reconfigured network, our simulation results indicate that the performance can be further improved by 10%-25% for Splash-2, PARSEC and SPEC CPU2006 benchmarks, whereas simulation results for a 256-core chip indicate a performance improvement of more than 25% while saving 23% of energy when compared to state-of-the-art on-chip electrical and optical networks.