Robust clock tree routing in the presence of process variations

Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock skew still limits postmanufacturing performance. Process-induced skew presents an ever-growing limitation for high-speed large-area clock networks. To achieve multigigahertz operation for high-end designs, clock networks must be constructed to tolerate variations in various interconnect parameters. This paper proposes a statistical centering-based clock routing algorithm that is built upon deferred merging embedding that greatly improves skew tolerance to interconnect variations. The algorithm achieves the improvement by the following ways: 1) choosing the best center measure which is dynamically based on the first three moments of the skew distribution and 2) designing for all sink pairs in the subtrees simultaneously. In addition, a variation-aware abstract topology generation algorithm is proposed in this paper. Experiments on benchmark circuits demonstrate that the proposed method reduces the number of skew violations by 12%-37%.