Reliability of memories built from unreliable components under data-dependent gate failures

Srdan Brkic, Predrag Ivaniš, Bane Vasić

Research output: Contribution to journalArticlepeer-review

7 Scopus citations


In this letter, we investigate fault-tolerance of memories built from unreliable cells. In order to increase thememory reliability, information is encoded by a low-density paritycheck (LDPC) code, and then stored. The memory content is updated periodically by the bit-flipping decoder, built also from unreliable logic gates, whose failures are transient and datadependent. Based on the expander property of Tanner graph of LDPC codes, we prove that the proposed memory architecture can tolerate a fixed fraction of component failures and consequently preserve all the stored information, if code length tends to infinity.

Original languageEnglish (US)
Article number7312924
Pages (from-to)2098-2101
Number of pages4
JournalIEEE Communications Letters
Issue number12
StatePublished - Dec 2015


  • Data-dependence
  • Faulty bit-flipping decoding
  • Low-density parity-check codes
  • Reliable memory architecture

ASJC Scopus subject areas

  • Modeling and Simulation
  • Computer Science Applications
  • Electrical and Electronic Engineering


Dive into the research topics of 'Reliability of memories built from unreliable components under data-dependent gate failures'. Together they form a unique fingerprint.

Cite this