TY - GEN
T1 - Realizing closed-loop, online tuning and control for configurable-cache embedded systems
T2 - 17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
AU - Badreldin, Islam
AU - Gordon-Ross, Ann
AU - Adegbija, Tosiron
AU - Alsafrjalaniz, Mohamad Hammam
N1 - Funding Information:
This work was supported by the National Science Foundation (CNS-0953447 and CNS-1718033).
Funding Information:
ACKNOWLEDGMENTS This work was supported by the National Science Foundation (CNS-0953447 and CNS-1718033). Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/8/7
Y1 - 2018/8/7
N2 - The cache subsystem is a major contributor to energy consumption in commercial microprocessors used in embedded systems. To reduce energy, designers can perform design space exploration (DSE) to determine a suitable cache configuration that matches system constraints and goals while minimizing energy consumption. Traditionally, this cache tuning step has been a static process where heuristics or analytical models are used to determine an optimal or near-optimal cache configuration prior to runtime given a known application, application set, or application domain. Even though the configuration may change during runtime for different phases of execution, the specific configuration for each phase remains fixed. This static nature is too restrictive for modern, complex embedded systems that are expected to operate under diverse, unknown operating environments, run unknown applications, and with vastly different user quality of experience (QoE) expectations (e.g., smart phones). Therefore, cache tuning must change from a static optimization process to a dynamic optimization process that adapts online during runtime transparently to the user/system needs. The key challenge is determining the configuration that adheres to QoE expectations while minimizing energy consumption without degrading the user experience during DSE. Despite the wealth of progress that has been made, the realization of a closed-loop, fully adaptive, online-Tunable cache subsystem still faces many challenges. In this paper, we review the progress made in the area of static and dynamic cache tuning, discuss the challenges that still exist in this area, and propose a predictionassisted control-Theoretic framework to address these challenges.
AB - The cache subsystem is a major contributor to energy consumption in commercial microprocessors used in embedded systems. To reduce energy, designers can perform design space exploration (DSE) to determine a suitable cache configuration that matches system constraints and goals while minimizing energy consumption. Traditionally, this cache tuning step has been a static process where heuristics or analytical models are used to determine an optimal or near-optimal cache configuration prior to runtime given a known application, application set, or application domain. Even though the configuration may change during runtime for different phases of execution, the specific configuration for each phase remains fixed. This static nature is too restrictive for modern, complex embedded systems that are expected to operate under diverse, unknown operating environments, run unknown applications, and with vastly different user quality of experience (QoE) expectations (e.g., smart phones). Therefore, cache tuning must change from a static optimization process to a dynamic optimization process that adapts online during runtime transparently to the user/system needs. The key challenge is determining the configuration that adheres to QoE expectations while minimizing energy consumption without degrading the user experience during DSE. Despite the wealth of progress that has been made, the realization of a closed-loop, fully adaptive, online-Tunable cache subsystem still faces many challenges. In this paper, we review the progress made in the area of static and dynamic cache tuning, discuss the challenges that still exist in this area, and propose a predictionassisted control-Theoretic framework to address these challenges.
KW - Cache configuration
KW - Heterogeneous multi core
KW - Runtime optimizations
KW - Self tuning
UR - http://www.scopus.com/inward/record.url?scp=85052134327&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85052134327&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2018.00136
DO - 10.1109/ISVLSI.2018.00136
M3 - Conference contribution
AN - SCOPUS:85052134327
SN - 9781538670996
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 719
EP - 725
BT - Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
PB - IEEE Computer Society
Y2 - 9 July 2018 through 11 July 2018
ER -