Real-Time Verification of Soft-Decision LDPC Coding for Burst Mode Upstream Reception in 50G-PON

Mingwei Yang, Linlin Li, Xiang Liu, Ivan B. Djordjevic

Research output: Contribution to journalArticlepeer-review

7 Scopus citations


Forward error correction (FEC) with high coding gain is needed to achieve PR30 (29 dB) link budget in 50G-PON. In particular, the stringent capacity and latency requirements of the 50G PON call for innovations in the design of FEC codes to go against the noise in the channel. In this paper, we propose a generic FPGA design for an adaptive irregular LDPC coding emulator that supports hard-decision, soft-decision, shortening, and puncturing. We evaluate the error-correction performance of the low-density parity-check (LDPC) forward-error correction (FEC) code that is currently under study by ITU-T's 50G-PON group for burst-mode upstream reception. Through experimental measurements based on a real-time FGPA platform, we found that soft-decision (SD) offers ∼1.3 dB more gross coding gain than hard-decision (HD). The SD LDPC performance is well maintained for non-uniform input bit error distributions where the errors are concentrated at the first 1/8 of each code word, corresponding to ∼44 ns (∼88 ns) for a 50-Gb/s (25-Gb/s) upstream signals. This indicates the suitability of the use of the SD-LDPC for burst-mode upstream reception in 50G-PON.

Original languageEnglish (US)
Article number8937482
Pages (from-to)1693-1701
Number of pages9
JournalJournal of Lightwave Technology
Issue number7
StatePublished - Apr 1 2020


  • 50G PON
  • FPGA
  • LDPC
  • burst error mode
  • hard decision
  • irregular code
  • scaled min-sum
  • soft decision

ASJC Scopus subject areas

  • Atomic and Molecular Physics, and Optics


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