Principle Hessian direction-based parameter reduction for interconnect networks with process variation

Alex Mitev, Michael Marefat, Dongsheng Ma, Janet Meiling Wang

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. To accurately consider both global and local process variations, a large number of random variables (or parameters) have to be incorporated into circuit models. This in turn raises the complexity of the circuit models. In this paper, we propose a principle Hessian direction-based parameter-reduction approach. This new approach relies on the impact of each parameter on circuit performance to decide whether keeping or reducing the parameter. Compared with the existing principle component analysis method, this performance based property provides us a significantly smaller set of parameters after reduction. The experimental results also support our conclusions. In interconnect cases, the proposed method reduces 70% of parameters. In some cases, for example, the mesh circuit in the current paper, the new approach leads to an 85% reduction. We also tested ISCAS benchmarks. In all cases, an average of 53% of reduction is observed with less than 3% error in the mean value and less than 8% error in the variation.

Original languageEnglish (US)
Article number5282514
Pages (from-to)1337-1347
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number9
StatePublished - Sep 2010


  • Principle Hessian directions (PHDs)
  • process variation
  • timing analysis

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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