Prefetching for improved bus wrapper performance in cores

Roman Lysecky, Frank Vahid

Research output: Contribution to journalArticlepeer-review

11 Scopus citations


Reuse of cores can reduce design time for systems-on-a-chip. Such reuse is dependent on being able to easily interface a core to any bus. To enable such interfacing, many propose separating a core's interface from its internals by using a bus wrapper. However, this separation can lead to a performance penalty when reading a core's internal registers. In this paper, we introduce prefetching, which is analogous to caching, as a technique to reduce or eliminate this performance penalty, involving a tradeoff with power and size. We describe the prefetching technique, classify different types of registers, describe our initial prefetching architectures and heuristics for certain classes of registers, and highlight experiments demonstrating the performance improvements and size/power tradeoffs. We further introduce a technique for automatically designing a prefetch unit that satisfies user-imposed register-access constraints. The technique benefits from mapping the prefetching problem to the well-known real-time process scheduling problem. We then extend the technique to allow user-specified register interdependencies, using a Petri net model, resulting in even mere efficient prefetch schedules.

Original languageEnglish (US)
Pages (from-to)58-90
Number of pages33
JournalACM Transactions on Design Automation of Electronic Systems
Issue number1
StatePublished - Jan 2002


  • Bus wrapper
  • Cores
  • Design reuse
  • Intellectual property
  • Interfacing
  • On-chip bus
  • PVCI
  • System-on-a-chip
  • VSIA

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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