TY - GEN
T1 - Pre-Fetching for Improved Core Interfacing
AU - Lysecky, Roman
AU - Vahid, Frank
AU - Givargis, Tony
AU - Patel, Rilesh
N1 - Funding Information:
6. Acknowledgements This work was supported by the National Science Foundation (CCR-9811164) and a Design Automation Conference Graduate Scholarship.
PY - 1999/11/1
Y1 - 1999/11/1
N2 - Reuse of cores can reduce design time for systems-on-a-chip. Such reuse is dependent on being able to easily interface a core to any bus. To enable such interfacing, many propose separating a core's interface from its internals. However, this separation can lead to a performance penalty when reading a core's internal registers. We introduce pre-fetching, which is analogous to caching, as a technique to reduce or eliminate this performance penalty, involving a tradeoff with power and size. We describe the pre-fetching technique, classify different types of registers, describe our initial pre-fetching architectures and heuristics for certain classes of registers, and highlight experiments demonstrating the performance improvements and size/power tradeoffs.
AB - Reuse of cores can reduce design time for systems-on-a-chip. Such reuse is dependent on being able to easily interface a core to any bus. To enable such interfacing, many propose separating a core's interface from its internals. However, this separation can lead to a performance penalty when reading a core's internal registers. We introduce pre-fetching, which is analogous to caching, as a technique to reduce or eliminate this performance penalty, involving a tradeoff with power and size. We describe the pre-fetching technique, classify different types of registers, describe our initial pre-fetching architectures and heuristics for certain classes of registers, and highlight experiments demonstrating the performance improvements and size/power tradeoffs.
KW - Cores
KW - intellectual property
KW - interfacing
KW - on-chip bus
KW - system-on-a-chip
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U2 - 10.1109/isss.1999.814260
DO - 10.1109/isss.1999.814260
M3 - Conference contribution
AN - SCOPUS:0009597420
T3 - Proceedings of the International Symposium on System Synthesis
BT - Proceedings of the 12th International Symposium on System Synthesis, ISSS 1999
PB - IEEE Computer Society
T2 - 12th International Symposium on System Synthesis, ISSS 1999
Y2 - 10 November 1999 through 12 November 1999
ER -