Pre-Fetching for Improved Core Interfacing

Roman Lysecky, Frank Vahid, Tony Givargis, Rilesh Patel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations


Reuse of cores can reduce design time for systems-on-a-chip. Such reuse is dependent on being able to easily interface a core to any bus. To enable such interfacing, many propose separating a core's interface from its internals. However, this separation can lead to a performance penalty when reading a core's internal registers. We introduce pre-fetching, which is analogous to caching, as a technique to reduce or eliminate this performance penalty, involving a tradeoff with power and size. We describe the pre-fetching technique, classify different types of registers, describe our initial pre-fetching architectures and heuristics for certain classes of registers, and highlight experiments demonstrating the performance improvements and size/power tradeoffs.

Original languageEnglish (US)
Title of host publicationProceedings of the 12th International Symposium on System Synthesis, ISSS 1999
PublisherIEEE Computer Society
ISBN (Electronic)076950356X, 9780769503561
StatePublished - Nov 1 1999
Event12th International Symposium on System Synthesis, ISSS 1999 - San Jose, United States
Duration: Nov 10 1999Nov 12 1999

Publication series

NameProceedings of the International Symposium on System Synthesis
VolumePart F129194
ISSN (Print)1080-1820


Other12th International Symposium on System Synthesis, ISSS 1999
Country/TerritoryUnited States
CitySan Jose


  • Cores
  • intellectual property
  • interfacing
  • on-chip bus
  • system-on-a-chip

ASJC Scopus subject areas

  • Hardware and Architecture


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