@inproceedings{01a33294645b490f84e2f6d91e31dae9,
title = "Post-routing analytical wirelength model for homogeneous FPGA architectures",
abstract = "We present a post-routing model that relates both logic and routing architecture parameters to wirelength for a homogeneous FPGA architecture. Our model relies on Rent's parameter generated from the pre-technology mapped netlist rather than post-placement netlist making it independent from optimization goal of the technology-mapping, clustering and placement stages of the FPGA CAD flow. We achieve an average mean absolute percentage error (MAPE) of 36% relative to the Verilog-to-Routing (VTR) based wire-length analysis using MCNC and VTR benchmarks, while state-of-the-art approach achieves a MAPE of 57%. This work forms the basis for implementing post-routing delay, routability and power models, since each can be expressed as a function of net length.",
keywords = "Analytical Model, FPGA, Post-routing Wire-length",
author = "Arpit Soni and Leow, {Yoon Kah} and Ali Akoglu",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018 ; Conference date: 03-12-2018 Through 05-12-2018",
year = "2019",
month = feb,
day = "13",
doi = "10.1109/RECONFIG.2018.8641724",
language = "English (US)",
series = "2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "David Andrews and Claudia Feregrino and Rene Cumplido and Dirk Stroobandt",
booktitle = "2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018",
}