Post-routing analytical wirelength model for homogeneous FPGA architectures

Arpit Soni, Yoon Kah Leow, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

We present a post-routing model that relates both logic and routing architecture parameters to wirelength for a homogeneous FPGA architecture. Our model relies on Rent's parameter generated from the pre-technology mapped netlist rather than post-placement netlist making it independent from optimization goal of the technology-mapping, clustering and placement stages of the FPGA CAD flow. We achieve an average mean absolute percentage error (MAPE) of 36% relative to the Verilog-to-Routing (VTR) based wire-length analysis using MCNC and VTR benchmarks, while state-of-the-art approach achieves a MAPE of 57%. This work forms the basis for implementing post-routing delay, routability and power models, since each can be expressed as a function of net length.

Original languageEnglish (US)
Title of host publication2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018
EditorsDavid Andrews, Rene Cumplido, Claudia Feregrino, Dirk Stroobandt
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728119687
DOIs
StatePublished - Jul 2 2018
Externally publishedYes
Event2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018 - Cancun, Mexico
Duration: Dec 3 2018Dec 5 2018

Publication series

Name2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018

Conference

Conference2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018
Country/TerritoryMexico
CityCancun
Period12/3/1812/5/18

Keywords

  • Analytical Model
  • FPGA
  • Post-routing Wire-length

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

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