As the multi-core architecture is becoming a prevailing high-performance chip design approach, power efficiency, limited bandwidth and low reliability have been recognized as major communication bottlenecks for on-chip networks (NOCs). To simultaneously tackle the above problems, we propose a three-dimensional integrated (3DI) photonic NOC architecture. This architecture is composed of the following layers: (i) the multi-core processor layer that host multiple heterogeneous processing cores together with corresponding local memories and network interfaces, (ii) multiple 3D memory layers that provide the bulk of on-chip memory, and (iii) photonic NOC layer. The photonic NOC layer is based on the optical cross-point switches (OXSs) implemented using active vertical coupler (AVC) structures. The use of this photonic NOC layer will provide ample bandwidth at reduced latencies along with low power consumption. The nanoscale photonic NOCs are sensitive to process variation and reliability issues. To deal with these problems, we proposed the use of LDPC codes with decoding based on simple majority-logic.