TY - JOUR
T1 - PhLock
T2 - A cache energy saving technique using phase-based cache locking
AU - Adegbija, Tosiron
AU - Gordon-Ross, Ann
N1 - Funding Information:
Manuscript received June 2, 2017; revised August 23, 2017; accepted September 25, 2017. Date of publication October 13, 2017; date of current version December 27, 2017. This work was supported in part by the National Science Foundation under Grant CNS-0953447. (Corresponding author: Tosiron Adegbija.) T. Adegbija is with the Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721 USA (e-mail: [email protected]).
Publisher Copyright:
© 2017 IEEE.
PY - 2018/1
Y1 - 2018/1
N2 - Caches are commonly used to bridge the processormemory performance gap in embedded systems. Since embedded systems typically have stringent design constraints imposed by physical size, battery capacity, and real-time deadlines much research focuses on cache optimizations, such as improved performance and/or reduced energy consumption. Cache locking is a popular cache optimization that loads and retains/locks selected memory contents from an executing application into the cache to increase the cache's predictability. Previous work has shown that cache locking also has the potential to improve cache energy consumption. In this paper, we introduce phasebased cache locking, PhLock, which leverages an application's varying runtime characteristics to dynamically select the locked memory contents to optimize cache energy consumption. Using a variety of applications from the SPEC2006 and MiBench benchmark suites, experimental results show that PhLock is promising for reducing both the instruction and data caches' energy consumption. As compared to a nonlocking cache, PhLock reduced the instruction and data cache energy consumption by an average of 5% and 39%, respectively, for SPEC2006 applications, and by 75% and 14%, respectively, for MiBench benchmarks.
AB - Caches are commonly used to bridge the processormemory performance gap in embedded systems. Since embedded systems typically have stringent design constraints imposed by physical size, battery capacity, and real-time deadlines much research focuses on cache optimizations, such as improved performance and/or reduced energy consumption. Cache locking is a popular cache optimization that loads and retains/locks selected memory contents from an executing application into the cache to increase the cache's predictability. Previous work has shown that cache locking also has the potential to improve cache energy consumption. In this paper, we introduce phasebased cache locking, PhLock, which leverages an application's varying runtime characteristics to dynamically select the locked memory contents to optimize cache energy consumption. Using a variety of applications from the SPEC2006 and MiBench benchmark suites, experimental results show that PhLock is promising for reducing both the instruction and data caches' energy consumption. As compared to a nonlocking cache, PhLock reduced the instruction and data cache energy consumption by an average of 5% and 39%, respectively, for SPEC2006 applications, and by 75% and 14%, respectively, for MiBench benchmarks.
KW - Adaptable computing
KW - Cache locking
KW - Configurable caches
KW - Dynamic optimization
KW - Energy savings
KW - Low-power embedded systems
KW - Persistent phases
KW - Phase-based tuning
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U2 - 10.1109/TVLSI.2017.2757477
DO - 10.1109/TVLSI.2017.2757477
M3 - Article
AN - SCOPUS:85049837216
SN - 1063-8210
VL - 26
SP - 110
EP - 121
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 1
ER -