Performance analysis of a high-speed dynamically reconfigurable LAN

In this paper, we present the design of a dynamically reconfigurable switch that will be used to build a high-speed multi-link ring local area network. Using FPGAs technology, switch reconfigurability can be exploited to implement different interconnection topologies and support different application requirements. We present two approaches to analyze the multi-link ring network performance. In the first approach, we develop an analytical model that uses the M/M/n and M/D/n queuing systems to study the virtual channels access delay. In this approach, the virtual channel occupancy probabilities are found using an infinite state Markove model. In the second approach, we introduce an analytical model based on a finite state Markov model developed for analyzing networks with virtual channels flow control. Simulation, using the OPNET tool, indicates that the second approach is more accurate in analyzing the behavior of the packet transfer time. Furthermore our performance analysis shows that the use of wormhole routing and virtual channel flow control improves the system throughput and decreases the packet transfer time.