TY - JOUR
T1 - Parallel optical interconnection network for address transactions in large-scale cache coherent symmetric multiprocessors
AU - Louri, Ahmed
AU - Kodi, Avinash Karanth
N1 - Funding Information:
Manuscript received September 25, 2002; revised January 20, 2003. This work was supported by the National Science Foundation under Grant CCR-0000518. The authors are with the Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ-85721 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/JSTQE.2003.814189
PY - 2003/3
Y1 - 2003/3
N2 - The authors address the primary limitation of bandwidth demands for address transaction in future cache coherent symmetric multiprocessors (SMPs). As a solution, the authors propose a scalable address subnetwork called symmetric multiprocessor network (SYMNET) in which address requests and snoop responses of shared memory multiprocessors are implemented optically. As the address phase of the transaction is linked to the address bandwidth, which is the major bottleneck in SMPs, they focus only on the address subnetwork in this paper. SYMNET has the capability to pipeline address requests from successive processors, which results in increasing the available address bandwidth and lowering the latency of the network. An optical token is implemented to achieve mutual exclusion to the shared channel. This enables collisionless broadcast of multiple address requests. The simultaneous insertion of multiple address requests into the address subnetwork complicates cache coherence. A modified coherence protocol, called COSYM, was introduced to solve the coherence problem. The authors evaluated SYMNET with a subset of Splash-2 benchmarks running from 4-32 processors. Their simulation studies have shown 10%-67% improvement in execution time for various applications. It is also shown that the average latency for a transaction to complete using COSYM was 85% better than the electrical case. An overview of the proposed optical implementation of SYMNET is presented along with the theoretical power budget and bit-error rate analysis. This analysis shows that SYMNET can scale up to hundreds of processors while still using fast snoopy-based cache coherence protocols and that additional performance gains may be attained with further improvement in optical device technology.
AB - The authors address the primary limitation of bandwidth demands for address transaction in future cache coherent symmetric multiprocessors (SMPs). As a solution, the authors propose a scalable address subnetwork called symmetric multiprocessor network (SYMNET) in which address requests and snoop responses of shared memory multiprocessors are implemented optically. As the address phase of the transaction is linked to the address bandwidth, which is the major bottleneck in SMPs, they focus only on the address subnetwork in this paper. SYMNET has the capability to pipeline address requests from successive processors, which results in increasing the available address bandwidth and lowering the latency of the network. An optical token is implemented to achieve mutual exclusion to the shared channel. This enables collisionless broadcast of multiple address requests. The simultaneous insertion of multiple address requests into the address subnetwork complicates cache coherence. A modified coherence protocol, called COSYM, was introduced to solve the coherence problem. The authors evaluated SYMNET with a subset of Splash-2 benchmarks running from 4-32 processors. Their simulation studies have shown 10%-67% improvement in execution time for various applications. It is also shown that the average latency for a transaction to complete using COSYM was 85% better than the electrical case. An overview of the proposed optical implementation of SYMNET is presented along with the theoretical power budget and bit-error rate analysis. This analysis shows that SYMNET can scale up to hundreds of processors while still using fast snoopy-based cache coherence protocols and that additional performance gains may be attained with further improvement in optical device technology.
KW - Cache coherence
KW - Parallel optical interconnects
KW - Scalable optical networks
KW - Symmetric multiprocessors (SMPs)
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U2 - 10.1109/JSTQE.2003.814189
DO - 10.1109/JSTQE.2003.814189
M3 - Article
AN - SCOPUS:0242661455
SN - 1077-260X
VL - 9
SP - 667
EP - 676
JO - IEEE Journal on Selected Topics in Quantum Electronics
JF - IEEE Journal on Selected Topics in Quantum Electronics
IS - 2
ER -