Abstract
Summary form only given, as follows. A parallel hardware implementation of the popular Hopfield neural network is described. The design utilizes the geometric arithmetic parallel processor (GAPP), an SIMD machine consisting of 72 processing elements. Memory requirements and processing times are analyzed based upon the number of nodes in the network and the number of exemplar patterns. Compared with other digital implementations, this design yields significant improvements in runtime performance.
| Original language | English (US) |
|---|---|
| Pages | 582 |
| Number of pages | 1 |
| State | Published - 1989 |
| Externally published | Yes |
| Event | IJCNN International Joint Conference on Neural Networks - Washington, DC, USA Duration: Jun 18 1989 → Jun 22 1989 |
Other
| Other | IJCNN International Joint Conference on Neural Networks |
|---|---|
| City | Washington, DC, USA |
| Period | 6/18/89 → 6/22/89 |
ASJC Scopus subject areas
- General Engineering