TY - GEN
T1 - PACT
T2 - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
AU - Gianelli, Sam
AU - Adegbija, Tosiron
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/20
Y1 - 2017/7/20
N2 - Due to the cache's significant impact on an embedded system, much research has focused on cache optimizations, such as reduced energy consumption or improved performance. However, throughout an embedded system's lifetime, the system may have different optimization priorities, due to variable operating conditions and requirements. Variable optimization priorities, embedded systems' stringent design constraints, and the fact that applications typically have execution phases with varying runtime resource requirements, necessitate new robust optimization techniques that can dynamically adapt to different optimization goals. In this paper, we present priority-aware phase-based cache tuning (PACT), which tunes an embedded system's cache at runtime in order to dynamically adhere the cache configurations to varying optimization goals (specifically EDP, energy, and execution time), application execution phases, and operating conditions, while accruing minimal runtime overheads.
AB - Due to the cache's significant impact on an embedded system, much research has focused on cache optimizations, such as reduced energy consumption or improved performance. However, throughout an embedded system's lifetime, the system may have different optimization priorities, due to variable operating conditions and requirements. Variable optimization priorities, embedded systems' stringent design constraints, and the fact that applications typically have execution phases with varying runtime resource requirements, necessitate new robust optimization techniques that can dynamically adapt to different optimization goals. In this paper, we present priority-aware phase-based cache tuning (PACT), which tunes an embedded system's cache at runtime in order to dynamically adhere the cache configurations to varying optimization goals (specifically EDP, energy, and execution time), application execution phases, and operating conditions, while accruing minimal runtime overheads.
KW - Configurable memory
KW - adaptable hardware
KW - cache memories
KW - cache tuning
KW - design space exploration
KW - low-power design
KW - low-power embedded systems
UR - http://www.scopus.com/inward/record.url?scp=85027277940&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85027277940&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2017.77
DO - 10.1109/ISVLSI.2017.77
M3 - Conference contribution
AN - SCOPUS:85027277940
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 403
EP - 408
BT - Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
A2 - Reis, Ricardo
A2 - Stan, Mircea
A2 - Huebner, Michael
A2 - Voros, Nikolaos
PB - IEEE Computer Society
Y2 - 3 July 2017 through 5 July 2017
ER -