Abstract
We have fabricated and tested an optically addressed, parallel electronic Reed-Solomon decoder for use with parallel access optical memories. A comparison with various serial implementations has demonstrated that for many instances of code block size and error correction capability, the parallel approach is superior from the perspectives of VLSI layout area and decoding latency. The demonstrated [15,9] Reed-Solomon parallel pipeline decoder operates on 60 bit input words and has been demonstrated at a clock rate of 5MHz yielding a demonstrated data rate of 300Mbps.
Original language | English (US) |
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Pages (from-to) | 543-553 |
Number of pages | 11 |
Journal | Proceedings of SPIE - The International Society for Optical Engineering |
Volume | 2026 |
DOIs | |
State | Published - Nov 9 1993 |
Externally published | Yes |
Event | Photonics for Processors, Neural Networks, and Memories 1993 - San Diego, United States Duration: Jul 11 1993 → Jul 16 1993 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Computer Science Applications
- Applied Mathematics
- Electrical and Electronic Engineering