TY - GEN
T1 - On the performance of SC-MMSE-FD equalization for fixed-point implementations
AU - Schwall, Michael
AU - Bose, Tamal
AU - Jondral, Friedrich K.
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/11/12
Y1 - 2014/11/12
N2 - A fixed-point implementation of a minimum mean square error (MMSE) based frequency domain (FD) equalizer with soft interference cancellation (SC) is studied. The equalizer additionally processes a priori information about the transmitted symbols and is used for turbo equalization. In this paper, we analyze the quantization and the clipping for different fixed-point representations and modulation schemes. The analysis allows to derive efficient representations for all symbols within the equalizer. This procedure is demonstrated for a generic system configuration featuring a 16-QAM. Finally, a fixed-point implementation in an integrated design environment for FPGAs verifies the theoretical studies and shows the device utilizations for different FPGAs that are embedded in current software defined radios. The results show, that on average 10 bits per symbol are required for a near-optimum equalization performance utilizing less than 8% area of state of the art FPGAs.
AB - A fixed-point implementation of a minimum mean square error (MMSE) based frequency domain (FD) equalizer with soft interference cancellation (SC) is studied. The equalizer additionally processes a priori information about the transmitted symbols and is used for turbo equalization. In this paper, we analyze the quantization and the clipping for different fixed-point representations and modulation schemes. The analysis allows to derive efficient representations for all symbols within the equalizer. This procedure is demonstrated for a generic system configuration featuring a 16-QAM. Finally, a fixed-point implementation in an integrated design environment for FPGAs verifies the theoretical studies and shows the device utilizations for different FPGAs that are embedded in current software defined radios. The results show, that on average 10 bits per symbol are required for a near-optimum equalization performance utilizing less than 8% area of state of the art FPGAs.
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U2 - 10.1109/ISTC.2014.6955093
DO - 10.1109/ISTC.2014.6955093
M3 - Conference contribution
AN - SCOPUS:84911867955
T3 - International Symposium on Turbo Codes and Iterative Information Processing, ISTC
SP - 97
EP - 101
BT - International Symposium on Turbo Codes and Iterative Information Processing, ISTC
PB - IEEE Computer Society
T2 - 2014 8th International Symposium on Turbo Codes and Iterative Information Processing, ISTC 2014
Y2 - 18 August 2014 through 22 August 2014
ER -