@inproceedings{e9b10a5c5cbc402781ce0b0cbfe04ec4,
title = "Nano-sim: A step wise equivalent conductance based statistical simulator for nanotechnology circuit design",
abstract = "New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology's sealing limitations. However, many such devices exhibit nonmonotonie I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes a new circuit simulation approach that can effectively simulate nanotechnology devices with uncertain input sources and negative differential resistance (NDR) problem. The experimental results show a 20-30 times speedup comparing with existing simulators.",
author = "Bharat Sukhwani and Uday Padmanabhan and Wang, {Janet M.}",
year = "2005",
doi = "10.1109/DATE.2005.221",
language = "English (US)",
isbn = "0769522882",
series = "Proceedings -Design, Automation and Test in Europe, DATE '05",
pages = "758--763",
booktitle = "Proceedings - Design, Automation and Test in Europe, DATE '05",
note = "Design, Automation and Test in Europe, DATE '05 ; Conference date: 07-03-2005 Through 11-03-2005",
}