TY - JOUR
T1 - Multidimensional and reconfigurable optical interconnects for high-performance computing (HPC) systems
AU - Kodi, Avinash Kodi
AU - Louri, Ahmed
N1 - Funding Information:
Manuscript received September 26, 2008, revised May 11, 2009. First published June 30, 2009; current version published September 10, 2009. This work was supported in part by the National Science Foundation under Grants CCR-0538945 and ECCS-0725765. A. K. Kodi is with the School of Electrical Engineering and Computer Science, Ohio University, Athens, OH 45701 USA (e-mail: [email protected]. edu; [email protected]). A. Louri is with the Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JLT.2009.2026187 Fig. 1. (a) Architectural overview of diagram of 1-D-RAPID.
PY - 2009/11/1
Y1 - 2009/11/1
N2 - The increasing demand for higher communication bandwidth, reduced power consumption, and increased reliability combined with fundamental electrical signalling limitations is leading the drive for optics as an interconnect technology of choice for high-performance computing (HPC) systems. However, failure in any optical link can completely disrupt communication by isolating processing nodes in HPC systems. Moreover, while static allocation of wavelengths (channels) provides every node with equal opportunity for communication, it can also lead to network congestion for nonuniform traffic patterns. In this paper, we propose a multidimensional optoelectronic architecture, called nD-reconfigurable, all-photonic interconnect for distributed and parallel systems (ndimensional-RAPID) where n can be 1, 2, or 3. nD-RAPID exploits optical architecture and technology design space that simultaneously tackles both fault-tolerance and dynamic bandwidth reallocation (DBR) of system architecture. Fault-tolerance in nD-RAPID is enabled through a multidimensional architecture. DBR is implemented by the row-column switching matrix using silicon-on-insulator (SOI)-based microring resonators that adapts to changes in communication patterns at runtime. Simulation results indicate that nD-RAPID outperformed other electrical networks for most traffic patterns. Results on DBR show that the proposed row-column switch organization significantly improves throughput and latency with a slight increase in electrical power consumption (∼0.4% for the worst case traffic).
AB - The increasing demand for higher communication bandwidth, reduced power consumption, and increased reliability combined with fundamental electrical signalling limitations is leading the drive for optics as an interconnect technology of choice for high-performance computing (HPC) systems. However, failure in any optical link can completely disrupt communication by isolating processing nodes in HPC systems. Moreover, while static allocation of wavelengths (channels) provides every node with equal opportunity for communication, it can also lead to network congestion for nonuniform traffic patterns. In this paper, we propose a multidimensional optoelectronic architecture, called nD-reconfigurable, all-photonic interconnect for distributed and parallel systems (ndimensional-RAPID) where n can be 1, 2, or 3. nD-RAPID exploits optical architecture and technology design space that simultaneously tackles both fault-tolerance and dynamic bandwidth reallocation (DBR) of system architecture. Fault-tolerance in nD-RAPID is enabled through a multidimensional architecture. DBR is implemented by the row-column switching matrix using silicon-on-insulator (SOI)-based microring resonators that adapts to changes in communication patterns at runtime. Simulation results indicate that nD-RAPID outperformed other electrical networks for most traffic patterns. Results on DBR show that the proposed row-column switch organization significantly improves throughput and latency with a slight increase in electrical power consumption (∼0.4% for the worst case traffic).
KW - Fault tolerance
KW - Optical interconnections
KW - Parallel processing
KW - Reconfigurable architectures
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U2 - 10.1109/JLT.2009.2026187
DO - 10.1109/JLT.2009.2026187
M3 - Article
AN - SCOPUS:70349417890
SN - 0733-8724
VL - 27
SP - 4634
EP - 4641
JO - Journal of Lightwave Technology
JF - Journal of Lightwave Technology
IS - 21
ER -