TY - GEN
T1 - Multi-mode low-latency software-defined error correction for data centers
AU - Ghaffari, Fakhreddine
AU - Akoglu, Ali
AU - Vasić, Bane
AU - Declercq, David
N1 - Funding Information:
This work was supported by the National Science Foundation under Grant ECCS-1500170 and CCF-1314147, the Indo-US Science and Technology Forum (IUSSTF) through the Joint Networked Center for Data Storage Research (JC-16-2014-US), and the French ANR project NAND under grant agreement ANR-15CE25-0006-01.
Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/14
Y1 - 2017/9/14
N2 - Flash memories are gaining prominence for utilizing in large scale data centers (DCs) due to their high memory density, low power consumption and heat dissipation, and high access speed characteristics. The rate of degradation for a flash memory is largely affected by the amount and frequency of the erase/write operations, which is a challenge in the DC context that serves dynamically changing workloads. Adaptive Error Correction Code (AECC) schemes have been introduced for changing the error correction algorithm based on the reliability state of the flash. In this study we show that hard decision (bit-flipping) and soft decision decoding (Belief Propagation) class of algorithms for Low Density Parity Check (LDPC) decoders complement each other for utilizing in the flash based DCs in order to meet the dynamically changing reliability level. We propose a new family of ECC to improve the reliability of flash memory. Our Monte-Carlo simulations and Field Programmable Gate Array (FPGA) based hardware implementation analysis show that LDPC decoders are suitable for balancing the throughput, decoding performance and reliability requirements in DCs.
AB - Flash memories are gaining prominence for utilizing in large scale data centers (DCs) due to their high memory density, low power consumption and heat dissipation, and high access speed characteristics. The rate of degradation for a flash memory is largely affected by the amount and frequency of the erase/write operations, which is a challenge in the DC context that serves dynamically changing workloads. Adaptive Error Correction Code (AECC) schemes have been introduced for changing the error correction algorithm based on the reliability state of the flash. In this study we show that hard decision (bit-flipping) and soft decision decoding (Belief Propagation) class of algorithms for Low Density Parity Check (LDPC) decoders complement each other for utilizing in the flash based DCs in order to meet the dynamically changing reliability level. We propose a new family of ECC to improve the reliability of flash memory. Our Monte-Carlo simulations and Field Programmable Gate Array (FPGA) based hardware implementation analysis show that LDPC decoders are suitable for balancing the throughput, decoding performance and reliability requirements in DCs.
KW - Data centers
KW - FPGA architecture
KW - Hardware complexity/decoding performance trade-off
KW - High-performance hard-decision and soft decision LDPC decoders
KW - Low-latency LDPC decoder
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U2 - 10.1109/ICCCN.2017.8038467
DO - 10.1109/ICCCN.2017.8038467
M3 - Conference contribution
AN - SCOPUS:85032261593
T3 - 2017 26th International Conference on Computer Communications and Networks, ICCCN 2017
BT - 2017 26th International Conference on Computer Communications and Networks, ICCCN 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 26th International Conference on Computer Communications and Networks, ICCCN 2017
Y2 - 31 July 2017 through 3 August 2017
ER -