@inproceedings{68b32fdd0c254c4991ec71b6f40d08cf,
title = "Multi-level tiling: M for the price of one",
abstract = "Tiling is a widely used loop transformation for exposing/-exploiting parallelism and data locality. High-performance implementations use multiple levels of tiling to exploit the hierarchy of parallelism and cache/register locality. Efficient generation of multi-level tiled code is essential for effective use of multi-level tiling. Parameterized tiled code, where tile sizes are not fixed but left as symbolic parameters can enable several dynamic and run-time optimizations. Previous solutions to multi-level tiled loop generation are limited to the case where tile sizes are fixed at compile time. We present an algorithm that can generate multi-level parameterized tiled loops at the same cost as generating single-level tiled loops. The efficiency of our method is demonstrated on several benchmarks. We also present a method-useful in register tiling-for separating partial and full tiles at any-arbitrary level of tiling. The code generator we have implemented is available as an open source tool. (c) 2007 ACM.",
keywords = "Data locality, Multi-level tiling, Parallelism, Parameterized code generation",
author = "Kim, \{Dae Gon\} and Lakshminarayanan Renganarayanan and Dave Rostron and Sanjay Rajopadhye and Strout, \{Michelle Mills\}",
year = "2007",
doi = "10.1145/1362622.1362691",
language = "English (US)",
isbn = "9781595937643",
series = "Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, SC'07",
booktitle = "Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, SC'07",
note = "2007 ACM/IEEE Conference on Supercomputing, SC'07 ; Conference date: 10-11-2007 Through 16-11-2007",
}