Multi-bit bit-flipping algorithm for column weight-4 LDPC codes

Xin Xiao, Bane V Vasic, Shu Lin

Research output: Contribution to journalConference articlepeer-review


Low-density parity-check (LDPC) codes with column weight-4 are widely used in many communication and storage systems. However, traditional hard decision decoding algorithms such as the bit-flipping (BF) algorithm suffer from error floor due to trapping sets in LDPC codes. In this paper, to lower error floor of the BF algorithm over the Binary Symmetric Channel (BSC), we design a set of decoding rules incorporated within the BF algorithm for column weight-4 LDPC codes. Given a column weight-4 LDPC code, the dominate error patterns of the BF algorithm are first specified, and according to the designed rules, additional bits at both variable nodes (VN) and check nodes (CN) provide more information for the BF algorithm to identify the dominate error patterns, so that the BF algorithm could deliberately flip some bits to break them. Simulation results show that the modified BF algorithm eliminates all 4-error patterns and lowers the Bit Error Rate (BER) for at least two orders of magnitude with a trivial increment of complexity.

Original languageEnglish (US)
JournalProceedings of the International Telemetering Conference
StatePublished - 2017
EventInternational Telemetering Conference 2017, ITC 2017 - Las Vegas, United States
Duration: Oct 23 2017Oct 26 2017

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Instrumentation
  • Computer Networks and Communications
  • Signal Processing


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