TY - JOUR
T1 - Monopoles Loaded with 3-D-Printed Dielectrics for Future Wireless Intrachip Communications
AU - Wu, Junqiang
AU - Kodi, Avinash Karanth
AU - Kaya, Savas
AU - Louri, Ahmed
AU - Xin, Hao
N1 - Funding Information:
Manuscript received April 06, 2017; revised September 11, 2017; accepted September 21, 2017. Date of publication October 2, 2017; date of current version November 30, 2017. This work was supported in part by the National Science Foundation under Grant ECCS-1408271, Grant CCF-1513923, Grant CCF-1054339 (CAREER), Grant CCF-1420718, Grant CCF-1318981, Grant CCF1513606, Grant CCF-1547034, Grant CCF-1547035, Grant CCF-1565273, and Grant CCF-1600820. (Corresponding author: Hao Xin.) J. Wu was with the Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721 USA. He is now with Maxim Integrated Inc., Beaverton, OR 97005 USA (e-mail: jqwu@email.arizona.edu).
Publisher Copyright:
© 1963-2012 IEEE.
PY - 2017/12
Y1 - 2017/12
N2 - We propose a novel antenna design enabled by 3-D printing technology for future wireless intrachip interconnects aiming at applications of multicore architectures and system-on-chips. In our proposed design we use vertical quarter-wavelength monopoles at 160 GHz on a ground plane to avoid low antenna radiation efficiency caused by the silicon substrate. The monopoles are surrounded by a specially designed dielectric property distribution. This additional degree of freedom in design enabled by 3-D printing technology is used to tailor the electromagnetic wave propagation. As a result, the desired wireless link gain is enhanced and the undesired spatial crosstalk is reduced. Simulation results show that the proposed dielectric loading approach improves the desired link gain by 8-15 dB and reduces the crosstalk by 9-23 dB from 155 to 165 GHz. As a proof-of-concept, a 60 GHz prototype is designed, fabricated, and characterized. Our measurement results match the simulation results and demonstrate 10-18 dB improvement of the desired link gain and 10-30 dB reduction in the crosstalk from 55 to 61 GHz. The demonstrated transmission loss of the desired link at a distance of 17 mm is only 15 dB, which is over 10 dB better than the previously reported work.
AB - We propose a novel antenna design enabled by 3-D printing technology for future wireless intrachip interconnects aiming at applications of multicore architectures and system-on-chips. In our proposed design we use vertical quarter-wavelength monopoles at 160 GHz on a ground plane to avoid low antenna radiation efficiency caused by the silicon substrate. The monopoles are surrounded by a specially designed dielectric property distribution. This additional degree of freedom in design enabled by 3-D printing technology is used to tailor the electromagnetic wave propagation. As a result, the desired wireless link gain is enhanced and the undesired spatial crosstalk is reduced. Simulation results show that the proposed dielectric loading approach improves the desired link gain by 8-15 dB and reduces the crosstalk by 9-23 dB from 155 to 165 GHz. As a proof-of-concept, a 60 GHz prototype is designed, fabricated, and characterized. Our measurement results match the simulation results and demonstrate 10-18 dB improvement of the desired link gain and 10-30 dB reduction in the crosstalk from 55 to 61 GHz. The demonstrated transmission loss of the desired link at a distance of 17 mm is only 15 dB, which is over 10 dB better than the previously reported work.
KW - 3-D printing
KW - antennas
KW - electromagnetic propagation
KW - interconnect
KW - intrachip communication
KW - multiprocessor interconnection
KW - network-on-chip (NoC)
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U2 - 10.1109/TAP.2017.2758400
DO - 10.1109/TAP.2017.2758400
M3 - Article
AN - SCOPUS:85030785426
VL - 65
SP - 6838
EP - 6846
JO - IEEE Transactions on Antennas and Propagation
JF - IEEE Transactions on Antennas and Propagation
SN - 0018-926X
IS - 12
M1 - 8055587
ER -