MirrorCache: An energy-efficient relaxed retention L1 STTRAM cache

Kyle Kuan, Tosiron Adegbija

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations


Spin-Transfer Torque RAM (STTRAM) is a promising alternative to SRAMs in on-chip caches, due to several advantages, including non-volatility, low leakage, high integration density, and CMOS compatibility. However, STTRAMs' wide adoption in resource-constrained systems is impeded, in part, by high write energy and latency. A popular approach to mitigating these overheads involves relaxing the STTRAM's retention time, in order to reduce the write latency and energy. However, this approach usually requires a dynamic refresh scheme to maintain cache blocks' data integrity beyond the retention time, and typically requires an external refresh buffer. In this paper, we propose mirrorCache-an energy-efficient, buffer-free refresh scheme. MirrorCache leverages the STTRAM cell's compact feature size, and uses an auxiliary segment with the same size as the logical cache size to handle the refresh operations without the overheads of an external refresh buffer. Our experiments show that, compared to prior work, mirrorCache can reduce the average cache energy by at least 39.7% for a variety of systems.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2019 - Proceedings of the 2019 Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Number of pages4
ISBN (Electronic)9781450362528
StatePublished - May 13 2019
Event29th Great Lakes Symposium on VLSI, GLSVLSI 2019 - Tysons Corner, United States
Duration: May 9 2019May 11 2019

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI


Conference29th Great Lakes Symposium on VLSI, GLSVLSI 2019
Country/TerritoryUnited States
CityTysons Corner


  • Cache
  • Emerging memory technologies
  • Energy efficient systems
  • Non-volatile memory
  • Retention time
  • Spin-transfer torque ram (sttram)
  • Write energy
  • Write latency

ASJC Scopus subject areas

  • Engineering(all)


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