TY - GEN
T1 - MirrorCache
T2 - 29th Great Lakes Symposium on VLSI, GLSVLSI 2019
AU - Kuan, Kyle
AU - Adegbija, Tosiron
N1 - Publisher Copyright:
© 2019 ACM.
PY - 2019/5/13
Y1 - 2019/5/13
N2 - Spin-Transfer Torque RAM (STTRAM) is a promising alternative to SRAMs in on-chip caches, due to several advantages, including non-volatility, low leakage, high integration density, and CMOS compatibility. However, STTRAMs' wide adoption in resource-constrained systems is impeded, in part, by high write energy and latency. A popular approach to mitigating these overheads involves relaxing the STTRAM's retention time, in order to reduce the write latency and energy. However, this approach usually requires a dynamic refresh scheme to maintain cache blocks' data integrity beyond the retention time, and typically requires an external refresh buffer. In this paper, we propose mirrorCache-an energy-efficient, buffer-free refresh scheme. MirrorCache leverages the STTRAM cell's compact feature size, and uses an auxiliary segment with the same size as the logical cache size to handle the refresh operations without the overheads of an external refresh buffer. Our experiments show that, compared to prior work, mirrorCache can reduce the average cache energy by at least 39.7% for a variety of systems.
AB - Spin-Transfer Torque RAM (STTRAM) is a promising alternative to SRAMs in on-chip caches, due to several advantages, including non-volatility, low leakage, high integration density, and CMOS compatibility. However, STTRAMs' wide adoption in resource-constrained systems is impeded, in part, by high write energy and latency. A popular approach to mitigating these overheads involves relaxing the STTRAM's retention time, in order to reduce the write latency and energy. However, this approach usually requires a dynamic refresh scheme to maintain cache blocks' data integrity beyond the retention time, and typically requires an external refresh buffer. In this paper, we propose mirrorCache-an energy-efficient, buffer-free refresh scheme. MirrorCache leverages the STTRAM cell's compact feature size, and uses an auxiliary segment with the same size as the logical cache size to handle the refresh operations without the overheads of an external refresh buffer. Our experiments show that, compared to prior work, mirrorCache can reduce the average cache energy by at least 39.7% for a variety of systems.
KW - Cache
KW - Emerging memory technologies
KW - Energy efficient systems
KW - Non-volatile memory
KW - Retention time
KW - Spin-transfer torque ram (sttram)
KW - Write energy
KW - Write latency
UR - http://www.scopus.com/inward/record.url?scp=85083168217&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85083168217&partnerID=8YFLogxK
U2 - 10.1145/3299874.3318022
DO - 10.1145/3299874.3318022
M3 - Conference contribution
AN - SCOPUS:85083168217
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 299
EP - 302
BT - GLSVLSI 2019 - Proceedings of the 2019 Great Lakes Symposium on VLSI
PB - Association for Computing Machinery
Y2 - 9 May 2019 through 11 May 2019
ER -