Mapping 1D-FFT on an energy efficient 3D FPGA-DRAM architecture

Peter Gadfort; Aravind Dasu; Ali Akoglu

doi:10.1109/E3S.2015.7336816

Mapping 1D-FFT on an energy efficient 3D FPGA-DRAM architecture

Peter Gadfort, Aravind Dasu, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The one-dimensional Fast Fourier Transform (1D-FFT) is a fast method of computing the Discrete Fourier Transform (DFT) that is pervasive in signal processing applications. In this paper we present details on the mapping of the 1D-FFT on a power efficient 3D FPGA-DRAM architecture [1], with four data sizes: 256pt, 1024pt, 4096pt and 32768pt to achieve 29 GFLOPs/W with a 65nm technology.

Original language	English (US)
Title of host publication	2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467385688
DOIs	https://doi.org/10.1109/E3S.2015.7336816
State	Published - Nov 24 2015
Event	4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Berkeley, United States Duration: Oct 1 2015 → Oct 2 2015

Publication series

Name	2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings

Other

Other	4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015
Country/Territory	United States
City	Berkeley
Period	10/1/15 → 10/2/15

Keywords

Adders
Computer architecture
Energy efficiency
Field programmable gate arrays
Ports (Computers)
Random access memory
Three-dimensional displays

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/E3S.2015.7336816

Cite this

Gadfort, P., Dasu, A., & Akoglu, A. (2015). Mapping 1D-FFT on an energy efficient 3D FPGA-DRAM architecture. In 2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings Article 7336816 (2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/E3S.2015.7336816

Mapping 1D-FFT on an energy efficient 3D FPGA-DRAM architecture. / Gadfort, Peter; Dasu, Aravind; Akoglu, Ali.
2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. 7336816 (2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Gadfort, P, Dasu, A & Akoglu, A 2015, Mapping 1D-FFT on an energy efficient 3D FPGA-DRAM architecture. in 2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings., 7336816, 2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015, Berkeley, United States, 10/1/15. https://doi.org/10.1109/E3S.2015.7336816

Gadfort P, Dasu A, Akoglu A. Mapping 1D-FFT on an energy efficient 3D FPGA-DRAM architecture. In 2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2015. 7336816. (2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings). doi: 10.1109/E3S.2015.7336816

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KW - Ports (Computers)

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Mapping 1D-FFT on an energy efficient 3D FPGA-DRAM architecture

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