Abstract
We present a robust process for fabricating high-Q, dispersion-engineered Si3N4 photonic chips using amorphous silicon hardmask etching with PECVD SiO2 cladding, achieving an intrinsic quality factor up to ∼ 17.5×106 and an average intrinsic quality factor of ∼ 13×106. We anticipate a further reduction in propagation loss through LPCVD SiO2 cladding.
| Original language | English (US) |
|---|---|
| State | Published - 2024 |
| Externally published | Yes |
| Event | CLEO: Science and Innovations in CLEO 2024, CLEO: S and I 2024 - Part of Conference on Lasers and Electro-Optics - Charlotte, United States Duration: May 5 2024 → May 10 2024 |
Conference
| Conference | CLEO: Science and Innovations in CLEO 2024, CLEO: S and I 2024 - Part of Conference on Lasers and Electro-Optics |
|---|---|
| Country/Territory | United States |
| City | Charlotte |
| Period | 5/5/24 → 5/10/24 |
ASJC Scopus subject areas
- Atomic and Molecular Physics, and Optics
- General Computer Science
- Space and Planetary Science
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
- Instrumentation