Abstract
A majority logic decoder made of unreliable logic gates, whose failures are transient and data-dependent, is analyzed. Based on a combinatorial representation of fault configurations a closed-form expression for the average bit error rate for a one-step majority logic decoder is derived, for a regular low-density parity-check (LDPC) code ensemble and the proposed failure model. The presented analysis framework is then used to establish bounds on the one-step majority logic decoder performance under the simplified probabilistic gate-output switching model. Based on the expander property of Tanner graphs of LDPC codes, it is proven that a version of the faulty parallel bit-flipping decoder can correct a fixed fraction of channel errors in the presence of data-dependent gate failures. The results are illustrated with numerical examples of finite geometry codes.
Original language | English (US) |
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Article number | 8013135 |
Pages (from-to) | 6295-6306 |
Number of pages | 12 |
Journal | IEEE Transactions on Information Theory |
Volume | 63 |
Issue number | 10 |
DOIs | |
State | Published - Oct 2017 |
Keywords
- Data-dependence
- LDPC codes
- faulty hardware
- majority logic decoding
- probabilistic gate-output switching model
ASJC Scopus subject areas
- Information Systems
- Computer Science Applications
- Library and Information Sciences