Lars: Logically adaptable retention time stt-ram cache for embedded systems

Kyle Kuan, Tosiron Adegbija

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

STT-RAMs have been studied as a promising alternative to SRAMs in embedded systems' caches and main memories. STT-RAMs are attractive due to their low leakage power and high density; STT-RAMs, however, also have drawbacks of long write latency and high dynamic write energy. A popular solution to this drawback relaxes the retention time to lower both write latency and energy, and uses a dynamic refresh scheme that refreshes data blocks to prevent them from prematurely expiring. However, the refreshes can incur overheads, thus limiting optimization potential. In addition, this solution only provides a single retention time, and cannot adapt to applications' variable retention time requirements. In this paper, we propose LARS (Logically Adaptable Retention Time STT-RAM) cache as a viable alternative for reducing the write energy and latency. LARS cache comprises of multiple STT-RAM units with different retention times, with only one unit on at a given time. LARS dynamically determines which STT-RAM unit to power on during runtime, based on executing applications' needs. Our experiments show that LARS cache is low-overhead, and can reduce the average energy and latency by 35.8% and 13.2%, respectively, as compared to the dynamic refresh scheme.

Original languageEnglish (US)
Title of host publicationProceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages461-466
Number of pages6
ISBN (Electronic)9783981926316
DOIs
StatePublished - Apr 19 2018
Event2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 - Dresden, Germany
Duration: Mar 19 2018Mar 23 2018

Publication series

NameProceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
Volume2018-January

Conference

Conference2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
Country/TerritoryGermany
CityDresden
Period3/19/183/23/18

Keywords

  • Adaptable hardware
  • Configurable memory
  • Low-power embedded systems
  • Retention time
  • Spin-Transfer torque ram (stt-ram) cache

ASJC Scopus subject areas

  • Safety, Risk, Reliability and Quality
  • Hardware and Architecture
  • Software
  • Information Systems and Management

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