TY - GEN
T1 - Inter-Architecture Portability of Artificial Neural Networks and Side Channel Attacks
AU - Gopale, Manoj
AU - Ditzler, Gregory
AU - Lysecky, Roman
AU - Roveda, Janet
N1 - Publisher Copyright:
© 2022 Owner/Author.
PY - 2022/6/6
Y1 - 2022/6/6
N2 - Side-channel attacks (SCA) have been studied for several decades, which resulted in many techniques that use statistical models to extract system information from side channels. More recently, machine learning has shown significant promise to advance the ability for SCAs to expose vulnerabilities. Artificial neural networks (ANN) can effectively learn nonlinear relationships between features within a side channel. In this paper, we propose a multi-architecture data aggregation technique to profile power traces for a system with an embedded processor that is based on three types of deep NNs, namely, multi-layer perceptrons (MLP), convolutional neural networks (CNN), and recurrent neural networks (RNN). This is one of the first works to explore the inter-architecture portability of NNs and SCAs. We demonstrate the robustness of the ANNs performing power-based SCAs on multiple architecture configurations with different architectural features, such as L1/L2 caches' size and associativity, and system memory size.
AB - Side-channel attacks (SCA) have been studied for several decades, which resulted in many techniques that use statistical models to extract system information from side channels. More recently, machine learning has shown significant promise to advance the ability for SCAs to expose vulnerabilities. Artificial neural networks (ANN) can effectively learn nonlinear relationships between features within a side channel. In this paper, we propose a multi-architecture data aggregation technique to profile power traces for a system with an embedded processor that is based on three types of deep NNs, namely, multi-layer perceptrons (MLP), convolutional neural networks (CNN), and recurrent neural networks (RNN). This is one of the first works to explore the inter-architecture portability of NNs and SCAs. We demonstrate the robustness of the ANNs performing power-based SCAs on multiple architecture configurations with different architectural features, such as L1/L2 caches' size and associativity, and system memory size.
KW - portability embedded security
KW - side channel attack
UR - http://www.scopus.com/inward/record.url?scp=85131694749&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85131694749&partnerID=8YFLogxK
U2 - 10.1145/3526241.3530356
DO - 10.1145/3526241.3530356
M3 - Conference contribution
AN - SCOPUS:85131694749
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 117
EP - 121
BT - GLSVLSI 2022 - Proceedings of the Great Lakes Symposium on VLSI 2022
PB - Association for Computing Machinery
T2 - 32nd Great Lakes Symposium on VLSI, GLSVLSI 2022
Y2 - 6 June 2022 through 8 June 2022
ER -