Innovative techniques for improved testability

Endre F. Sarkany, Robert F. Lusch

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Three independent topics which illustrate innovative methods for improving testability are described. First, a technique which utilizes a card logic tester as a vehicle for evaluating the effectiveness of new chip-level tests is described. This technique allows rapid implementation and verification of various test algorithms as chip failure mechanisms are discovered. Second, a methodology which combines simulation data with the capabilities of a tester language to provide early verification of the AC characteristics of components is presented. Third and finally, the authors consider tester language limitations and how adjustments can be made to component timing specifications to overcome these restrictions. These techniques were successfully implemented using Programming Language for Testing (PLT). With these methods, the testability and hence the quality of recent IBM products were improved in a cost-effective manner.

Original languageEnglish (US)
Title of host publicationDigest of Papers - International Test Conference
PublisherPubl by IEEE
Number of pages6
ISBN (Print)0818620641
StatePublished - Sep 1990
Externally publishedYes
EventProceedings - International Test Conference 1990 - Washington, DC, USA
Duration: Sep 10 1990Sep 14 1990

Publication series

NameDigest of Papers - International Test Conference
ISSN (Print)0743-1686


OtherProceedings - International Test Conference 1990
CityWashington, DC, USA

ASJC Scopus subject areas

  • Engineering(all)


Dive into the research topics of 'Innovative techniques for improved testability'. Together they form a unique fingerprint.

Cite this