Hierarchical built-in self-testing and FPGA based healing methodology for system-on-a-chip

Advances in VLSI technology have led to fabrication of chips with number of transistors reaching a billion figure and projected to be 10 billion in the near future. Affordable and fault tolerant solutions transparent to applications with minimal hardware overhead in the micro architecture are necessary to mitigate component level errors for emerging system-on-chip (SoC) platforms. Paper addresses built-in self-testing and fault detection, isolation and recovery capabilities to offer 100% system availability. We reduce the complexity of testing with a two-phase hierarchical approach that first detects fault at component level and then locates it at sub-component level. Proposed approach reduces the amount of test patterns required to detect a fault. Secondly size of the circuit to be replaced is greatly reduced. We then introduce a novel self-healing on the fly mechanism for SoC using field programmable gate array (FPGA) technology that localizes and isolates the faulty area and then replaces the functionality through partial configuration of the FPGA. Even though isolation mechanism requires additional control circuitry, overall area overhead is greatly reduced by eliminating the need for redundant components on the chip. In case of no fault, FPGA resources are available for additional functionality that might be required in time.