Hard-decision decoding of LDPC codes under timing errors: Overview and new results

Srdan Brkic, Predrag Ivanis, Bane Vasić

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations


This paper contains a survey on iterative decoders of low-density parity-check (LDPC) codes built form unreliable logic gates. We assume that hardware unreliability comes from supply voltage reduction, which causes probabilistic gate failures, called timing errors. We are able to demonstrate robustness of simple Gallager B decoder to timing errors, when applied on codes free of small trapping sets, as well as positive effects that timing errors have on the decoding of codes with contain small trapping sets. Furthermore, we show that concept of guaranteed error correction can be applied to the decoders made partially from unreliable components. In contrast to the decoding under uncorrelated gate failures, we prove that bit-flipping decoding under timing errors can achieve arbitrary low error probability. Consequently, we formulate condition sufficient that memory architecture, which employs bit-flipping decoder, preserved all stored information.

Original languageEnglish (US)
Title of host publication2017 25th Telecommunications Forum, TELFOR 2017 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages8
ISBN (Electronic)9781538630723
StatePublished - Jan 5 2018
Event25th Telecommunications Forum, TELFOR 2017 - Belgrade, Serbia
Duration: Nov 21 2017Nov 22 2017

Publication series

Name2017 25th Telecommunications Forum, TELFOR 2017 - Proceedings


Other25th Telecommunications Forum, TELFOR 2017


  • Bit-flipping
  • Gallager B
  • data-dependence
  • fault-tolerance
  • low-density parity-check codes
  • timing errors

ASJC Scopus subject areas

  • Signal Processing
  • Safety, Risk, Reliability and Quality
  • Computer Networks and Communications


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