HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems

Kyle Kuan, Tosiron Adegbija

Research output: Contribution to journalArticlepeer-review

21 Scopus citations


Spin-Transfer Torque RAM (STT-RAM) is widely considered a promising alternative to SRAM in the memory hierarchy due to STT-RAM's non-volatility, low leakage power, high density, and fast read speed. The STT-RAM's small feature size is particularly desirable for the last-level cache (LLC), which typically consumes a large area of silicon die. However, long write latency and high write energy still remain challenges of implementing STT-RAMs in the CPU cache. An increasingly popular method for addressing this challenge involves trading off the non-volatility for reduced write speed and write energy by relaxing the STT-RAM's data retention time. However, in order to maximize energy saving potential, the cache configurations, including STT-RAM's retention time, must be dynamically adapted to executing applications' variable memory needs. In this paper, we propose a highly adaptable last level STT-RAM cache (HALLS) that allows the LLC configurations and retention time to be adapted to applications' runtime execution requirements. We also propose low-overhead runtime tuning algorithms to dynamically determine the best (lowest energy) cache configurations and retention times for executing applications. Compared to prior work, HALLS reduced the average energy consumption by 60.57 percent in a quad-core system, while introducing marginal latency overhead.

Original languageEnglish (US)
Article number8721116
Pages (from-to)1623-1634
Number of pages12
JournalIEEE Transactions on Computers
Issue number11
StatePublished - Nov 1 2019
Externally publishedYes


  • Spin-transfer torque RAM (STT-RAM) cache
  • adaptable hardware
  • computer architecture
  • configurable memory
  • energy-efficient
  • last level cache
  • low-power systems
  • multicore systems
  • retention time
  • runtime adaptable systems

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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