TY - GEN
T1 - Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures
AU - Brkic, Srdan
AU - Ivanis, Predrag
AU - Vasic, Bane
N1 - Funding Information:
This work was supported by the Seventh Framework Programme of the European Union, under Grant Agreement number 309129 (i-RISC project), Serbian Ministry of Science under project TR32028, NSF under Grants CCF-0963726, CCF-1314147 and ECCS-1500170
Publisher Copyright:
© 2016 IEEE.
PY - 2016/8/10
Y1 - 2016/8/10
N2 - In this paper we analyze the effect of hardware unreliability to performance of bit-flipping decoders of low-density parity-check (LDPC) codes. We apply expander arguments to show that the simple parallel bit flipping decoder, built partially from faulty gates, can correct a linear fraction of worst case channel errors, when gate failures are correlated and dependent on the switching activity of logic gates. In addition, we provide a lower bound on the guaranteed error correction of LDPC codes with left degree of at least eight.
AB - In this paper we analyze the effect of hardware unreliability to performance of bit-flipping decoders of low-density parity-check (LDPC) codes. We apply expander arguments to show that the simple parallel bit flipping decoder, built partially from faulty gates, can correct a linear fraction of worst case channel errors, when gate failures are correlated and dependent on the switching activity of logic gates. In addition, we provide a lower bound on the guaranteed error correction of LDPC codes with left degree of at least eight.
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U2 - 10.1109/ISIT.2016.7541561
DO - 10.1109/ISIT.2016.7541561
M3 - Conference contribution
AN - SCOPUS:84985930799
T3 - IEEE International Symposium on Information Theory - Proceedings
SP - 1561
EP - 1565
BT - Proceedings - ISIT 2016; 2016 IEEE International Symposium on Information Theory
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 IEEE International Symposium on Information Theory, ISIT 2016
Y2 - 10 July 2016 through 15 July 2016
ER -